package hardcaml

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package hardcaml
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A collection of common Xilinx Vivado attributes.

val async_reg : bool -> t

Inform Vivado that a registers data input is asychronous to it's clock.

val dont_touch : bool -> t

Instruct the synthesizer and place & route tools to keep the node. Cannot be applied to a port.

val fsm_encoding : [ `auto | `gray | `johnson | `none | `one_hot | `sequential ] -> t

Select encoding of finite state machine. Apply to state register.

val mark_debug : bool -> t

Export net for debugging with chipscope.

module Ram_style : sig ... end
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