A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.
In Verilog they are called parameterss and in VHDL they are called generics.
module Std_logic : sig ... end9-state VHDL std_logic enumeration
module Std_logic_vector : sig ... endmodule Bit_vector : sig ... endmodule Value : sig ... endval compare : t -> t -> Base.Int.tval sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.tinclude Base.Equal.S with type t := tval equal : t Base.Equal.equalmodule Unstable : sig ... endval create : name:Base.String.t -> value:Value.t -> tval find_name : t Base.List.t -> Parameter_name.t -> Value.t Base.Option.tval find_name_exn : t Base.List.t -> Parameter_name.t -> Value.tval is_subset : t Base.List.t -> t Base.List.t -> Base.Bool.tis_subset ts1 ts2 returns true iff every t in ts1 is in ts2.
val sort_by_name : t Base.List.t -> t Base.List.t