hardcaml v0.13.0 · OCaml Package

Creation and manipulation of hardware circuits

type t

circuit data structure

val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t

type 'a with_create_options =
  ?detect_combinational_loops:Base.Bool.t ->
  ?normalize_uids:Base.Bool.t ->
  'a

with_create_options specifies the optional arguments that can be supplied to create_exn.

detect_combinational_loops determines whether create_exn ensures that there is no path from a signal to itself that does not pass through a register or memory.

normalize_uids determines whether create_exn renumbers the uids of all signals in the circuit starting at one. Uid normalization ensures that circuits will print the same (as sexps or rtl) regardless of the environment in which they are constructed (in particular with regard to the global uid generator).

val create_exn : 
  (name:Base.String.t -> Signal.t Base.List.t -> t) with_create_options

create circuit data structure

val inputs : t -> Signal.t Base.List.t

return circuit inputs

val outputs : t -> Signal.t Base.List.t

return circuit outputs

val signal_graph : t -> Signal_graph.t

val name : t -> Base.String.t

return circuit name

val with_name : t -> name:Base.String.t -> t

Return identical circuit except for the name.

val is_input : t -> Signal.t -> Base.Bool.t

is the signal an input to the circuit

val is_output : t -> Signal.t -> Base.Bool.t

is the signal an output of the circuit

val find_signal_exn : t -> Signal.Uid.t -> Signal.t

val set_phantom_inputs : t -> (Base.String.t * Base.Int.t) Base.List.t -> t

For internal use. Add phantom input ports to the circuit when writing RTL. This can be necessary to ensure Interface based input specifications match those discovered when traversing the hardware design from its outputs. It is especially important when working with hierarchical designs.

val phantom_inputs : t -> (Base.String.t * Base.Int.t) Base.List.t

module Signal_map : sig ... end

Map of uids to Signal.ts.

val signal_map : t -> Signal_map.t

Get map of uids to Signal.ts.

val fan_out_map : t -> Signal.Uid_set.t Signal.Uid_map.t

Compute and return a Fan_out_map.t. The computation is lazy and only performed the first time fan_out_map is called.

val fan_in_map : t -> Signal.Uid_set.t Signal.Uid_map.t

Compute and return a Fan_in_map.t. The computation is lazy and only performed the first time fan_in_map is called.

val structural_compare : ?check_names:Base.Bool.t -> t -> t -> Base.Bool.t

compare 2 circuits to see if they are the same

module Create_options : sig ... end

Create_options is a record with one field for each with_create_options argument. It allows one to define a function of type _ with_create_options that takes the same optional arguments as create_exn and to pass those options on to create_exn, without every having to directly refer to any of the arguments. This makes wrapper code robust to changes in what the optional arguments are. Here is the usage idiom:

val with_create_options : (Create_options.t -> 'a) -> 'a with_create_options

val call_with_create_options : 'a with_create_options -> Create_options.t -> 'a

module Port_checks : sig ... end

Check if the ports specified in the interface match those defined in the circuit.

module With_interface (I : Interface.S) (O : Interface.S) : sig ... end

package hardcaml