9-state VHDL std_logic enumeration
val compare : t -> t -> Base.Int.tval all : t Base.List.tval sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.tval u : tval x : tval l0 : tval l1 : tval z : tval w : tval l : tval h : tval don't_care : tmodule Variants : sig ... endinclude Base.Equal.S with type t := tval equal : t Base.Equal.equalmodule Unstable : sig ... endval to_int : t -> Base.Int.tProvide the index of t in textual order. When passing a std_logic parameter from verilog to vhdl, we need to encode this type into an integer. For example, L1 = 4'd3.
val of_char_exn : Base.Char.t -> tThe OCaml char used in of_char and to_char is the same as used in VHDL.
val to_char : t -> Base.Char.t