package diffast-langs-verilog

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package diffast-langs-verilog
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Module Verilog_base.V_treeSource

module Sourcecode = Diffast_core.Sourcecode
module Fname = Langs_common.Fname
module Astloc = Langs_common.Astloc
Sourcemodule P = Printer
Sourcemodule L = V_label
Sourceval sprintf : ('a, unit, string) format -> 'a
Sourceval conv_loc : L.Ast.Loc.t -> L.Loc.t
Sourceval set_loc : < data : < set_loc : L.Loc.t -> 'a.. >.. > -> L.Ast.Loc.t -> 'a
module Tree : sig ... end
Sourceval of_ast : Diffast_core.Parser_options.c -> < comment_regions : (int * int) list ; ignored_regions : (int * int) list ; lines_read : int ; missed_regions : (int * int) list ; root : < children : 'a list ; label : L.t ; lloc : < get_level : int ; get_loc_of_level : int -> Astloc.t.. > ; loc : L.Ast.Loc.t.. > as 'a.. > -> Tree.c
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