package diffast-langs-verilog

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package diffast-langs-verilog
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Module V_label.SequenceExpressionSource

include module type of struct include Ls.SequenceExpression end
Sourcetype t = Verilog_parsing.Labels.SequenceExpression.t =
  1. | Concat
  2. | Repetition
  3. | OnMatch
  4. | And
  5. | Or
  6. | Intersect
  7. | First_match
  8. | Throughout
  9. | Within
  10. | Clocking
Sourceval to_string : t -> string
Sourceval to_simple_string : t -> string
Sourceval to_tag : t -> string * 'a list
Sourceval get_identifier : 'a -> 'b
Sourceval to_short_string : t -> string
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