package diffast-langs-verilog-parsing

You can search for identifiers within the package.

in-package search v0.2.0

package diffast-langs-verilog-parsing

diffast-langs-verilog-parsing
- README
- Library diffast-langs-verilog-parsing
  - Verilog_parsing
    
    Ast
    
    Layeredloc
    
    Astloc
    
    Ast_base
    
    Loc
    
    LLoc
    
    L
    
    node
    
    c
    
    Common
    
    Xprint
    
    Parserlib_base
    
    PB
    
    Context
    
    Astloc
    
    Loc
    
    stack
    
    Label
    
    Label_common
    
    XML
    
    Xstring
    
    Labels
    
    OverloadOperator
    
    AssignmentOperator
    
    IncOrDecOperator
    
    UnaryOperator
    
    BinaryOperator
    
    TimingCheck
    
    SystemTask
    
    Qualifier
    
    NetType
    
    PortDirection
    
    Gate
    
    DataType
    
    Expression
    
    EventExpression
    
    PropertyExpression
    
    SequenceExpression
    
    JoinSpec
    
    Statement
    
    CompilerDirective
    
    Strength
    
    SimpleImmediateAssertion
    
    DeferredImmediateAssertion
    
    ConcurrentAssertion
    
    ModuleSpec
    
    AlwaysSpec
    
    BinsSpec
    
    Lib
    
    Storage
    
    Parserlib_base
    
    Astloc
    
    Loc
    
    Aux
    
    PB
    
    C
    
    parser_c
    
    Macro
    
    Macro_base
    
    Loc
    
    table
    
    Parser
    
    Make
    
    MenhirInterpreter
    
    Incremental
    
    Parser_aux
    
    Fname
    
    Env_base
    
    L
    
    env
    
    STATE_T
    
    F
    
    Printer
    
    Scanner
    
    Parserlib_base
    
    Astloc
    
    Loc
    
    Aux
    
    PB
    
    TB
    
    F
    
    TBF
    
    Tokens
    
    Tok
    
    U
    
    Loc
    
    Aux
    
    T
    
    A
    
    buffer_base
    
    buffer
    
    branching_buffer
    
    c
    
    tokensource
    
    U
    
    Loc
    
    Aux
    
    T
    
    A
    
    c
    
    Source
    
    Source_base
    
    c
    
    Token
    
    Parserlib_base
    
    Astloc
    
    Loc
    
    PB
    
    F
    
    Tokenbuffer
    
    Xlist
    
    Xqueue
    
    Xstring
    
    Loc
    
    Aux
    
    L
    
    C
    
    F
    
    Tokens
    
    Tok
    
    U
    
    Loc
    
    Aux
    
    T
    
    A
    
    buffer_base
    
    buffer
    
    branching_buffer
    
    c
    
    tokensource
    
    Tokens
    
    Make
    
    MenhirInterpreter
    
    Tokens_
    
    T
    
    MenhirInterpreter
    
    MenhirInterpreter
    
    Ulexer
    
    Xfile
    
    Astloc
    
    Loc
    
    Ls
    
    F
    
    Loc
    
    Aux
    
    T
- Sources
  - diffast-langs-verilog-parsing
    
    ast.ml
    
    common.ml
    
    context.ml
    
    label.ml
    
    label_common.ml
    
    labels.ml
    
    lib.ml
    
    macro.ml
    
    parser.ml
    
    parser_aux.ml
    
    printer.ml
    
    scanner.ml
    
    source.ml
    
    token.ml
    
    tokenbuffer.ml
    
    tokens.ml
    
    tokens_.ml
    
    ulexer.ml
    
    verilog_parsing.ml

Legend:
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Library
Module
Module type
Parameter
Class
Class type
Source

Module `U.Aux`Source

Sourceval lexing_pos_start : Sedlexing.lexbuf -> Lexing.position

Sourceval lexing_pos_end : Sedlexing.lexbuf -> Lexing.position

val parse_warning : 
  ?out:out_channel ->
  ?head:string ->
  Lexing.position ->
  Lexing.position ->
  ('a, out_channel, unit, unit) format4 ->
  'a

val parse_error : 
  Lexing.position ->
  Lexing.position ->
  ('a, unit, string, Ast.node) format4 ->
  'a

val parse_error_loc : 
  Langs_common.Astloc.t ->
  ('a, unit, string, Ast.node) format4 ->
  'a

Sourceval parse_failure_loc : Verilog_parsing.Ast.Loc.t -> string -> 'a

Sourceval get_loc_for_lex : Sedlexing.lexbuf -> Verilog_parsing.Ast.Loc.t

val check_error : 
  < children : 'a list
    ; label : Label.t
    ; loc : Langs_common.Astloc.t.. > as 'a ->
  unit

val lloc_of_poss : 
  Lexing.position ->
  Lexing.position ->
  Verilog_parsing.Ast.Layeredloc.c

Sourceval make_error_node : Lexing.position -> Lexing.position -> Ast.node

Sourceval register_vartype : string -> unit

Sourceval register_class : string -> unit

Sourceval register_type : string -> unit

Sourceval register_package : string -> unit

Sourceval register_property : string -> unit

Sourceval register_covergroup : string -> unit

Sourceval register_clocking : string -> unit

Sourceval register_extern_method : string -> unit

Sourceval register_interface : string -> unit

Sourceval begin_package_scope : Common.identifier -> unit

Sourceval begin_class_scope : Common.identifier -> unit

Sourceval begin_function_scope : Common.identifier -> unit

Sourceval begin_scope : unit -> unit

Sourceval end_scope : unit -> unit

Sourceval import_one : Common.identifier -> Common.identifier -> unit

Sourceval import_any : Common.identifier -> unit

val lookup_identifier : 
  string ->
  Verilog_parsing__Parser_aux.identifier_attribute list

Sourceval set_vartype_type : unit -> unit

Sourceval reset_vartype : unit -> unit

val import_pkg_cls_scope : 
  (Common.identifier option * Common.identifier list) ->
  unit

val node_to_loc : 
  < lloc : 
    < to_loc : ?cache:Langs_common.Fname.ext_cache_t option -> unit -> 'a.. >.. > ->
  'a

val node_to_lexposs : 
  < lloc : 
    < to_loc : 
      ?cache:Langs_common.Fname.ext_cache_t option ->
      unit ->
      Verilog_parsing.Ast.Loc.t.. >.. > ->
  Lexing.position * Lexing.position