package hardcaml_event_driven_sim

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Parameters
Signature

hardcaml_event_driven_sim
- Hardcaml_event_driven_sim
  - Four_state_logic
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Logic
    
    S
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Make
    
    Logic
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Ops
    
    Vcd
    
    With_interface
    
    Input
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    Logic
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Ops
    
    Output
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Ops
    
    Make
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    S
  - Port
  - Two_state_logic
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Vcd
    
    Make
    
    Logic
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Waveterm
    
    Events
    
    Expect
    
    Make
    
    Logic
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Render
    
    Bounds
    
    Make
    
    G
    
    Static
    
    R
    
    Styles
    
    Serialize
    
    Wave
    
    Waveform
    
    Waves
    
    Config
hardcaml_event_driven_sim.kernel
- Event_driven_sim
  - Mini_async
    
    Deferred
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Ivar
  - Simulator
    
    Async
    
    Change_monitor
    
    Debug
    
    Expert
    
    Process
    
    Signal
    
    Signal_id
    
    Value_S
    
    Version_signal

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Module
Module type
Parameter
Class
Class type

Parameters

module Comb : Logic.S

Signature

type t

val processes : t -> Event_driven_sim.Simulator.Process.t list

val find_sim_signal : 
  t ->
  Hardcaml.Signal.t ->
  Comb.t Event_driven_sim.Simulator.Signal.t

Find the simulation signal associated with the given Hardcaml signal. Raises if the signal does not exist within the circuit.

val fake_sim_signal : 
  t ->
  Hardcaml.Signal.t ->
  Comb.t Event_driven_sim.Simulator.Signal.t

Construct a fake simulation signal for the given Hardcaml signal.

val circuit_to_processes : 
  ?delay:(Hardcaml.Signal.t -> int) ->
  ?external_insts:
    (Hardcaml.Signal.t ->
      inputs:Comb.t Event_driven_sim.Simulator.Signal.t list ->
      Comb.t Event_driven_sim.Simulator.Signal.t) ->
  Hardcaml.Circuit.t ->
  t

Compiles Hardcaml circuit into a Event_driven_sim process list. Returns the list and a mapping from Hardcaml signals into Event_driven_sim signals.

For every signal, delay should return the simulation time it takes to compute value for a given signal. Default is to have no delay.