package hardcaml_axi

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package hardcaml_axi
Legend:
Library
Module
Module type
Parameter
Class
Class type

Parameters

module Master_to_slave : sig ... end
module Slave_to_master : sig ... end

Signature

type result = {
  1. write_values : Hardcaml.Signal.t Hardcaml.With_valid.t Base.list;
  2. read_enables : Hardcaml.Signal.t Base.list;
}
val sexp_of_result : result -> Sexplib0.Sexp.t
type pipelined_read_depth = {
  1. external_cycles : Base.int;
  2. internal_mux_cycles : Base.int;
}

Creates a register bank.

let { slave; write_values } =
  create ~reg_spec ~master ~write_modes ~read_values

write_modes specifies what behavior the corresponding write_value should have: hold the value written, or toggle back to some known value after 1 cycle.

write_values can be connected to read_values to create a read/write register.

Writes ignore master.write_byte_en, therefore only aligned 32 bit transfers are fully supported.

clear_write_values clears write registers whose mode is configured with mode internal_clear = true.

val create : ?pipelined_read_depth:pipelined_read_depth -> Hardcaml.Reg_spec.t -> clear_write_values:Hardcaml.Signal.t -> master:Hardcaml.Signal.t Master_to_slave.t -> write_modes:Register_mode.t Base.list -> read_values:Hardcaml.Signal.t Base.list -> t
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