Definition of clock, reset and clear signals for sequential logic (ie registers).
include module type of struct include Signal.Reg_spec_ endReg_spec_ is a register specification. It is named Reg_spec_ rather than Reg_spec so that people consistently use the name Hardcaml.Reg_spec rather than Hardcaml.Signal.Reg_spec_.
type t = Signal.registerval sexp_of_t : t -> Sexplib0.Sexp.tval create :
?clear:Signal.signal ->
?reset:Signal.signal ->
Base.unit ->
clock:Signal.signal ->
tval override :
?clock:Signal.signal ->
?clock_edge:Edge.t ->
?reset:Signal.signal ->
?reset_edge:Edge.t ->
?reset_to:Signal.signal ->
?clear:Signal.signal ->
?clear_level:Level.t ->
?clear_to:Signal.signal ->
?global_enable:Signal.signal ->
t ->
tval clock : t -> Signal.signalval clear : t -> Signal.signalval reset : t -> Signal.signal