package hardcaml

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package hardcaml
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Module Hardcaml.Reg_specSource

Definition of clock, reset and clear signals for sequential logic (ie registers).

include module type of struct include Signal.Reg_spec_ end
Sourceval sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
Sourceval create : ?clear:Signal.signal -> ?reset:Signal.signal -> Base.Unit.t -> clock:Signal.signal -> t
Sourceval override : ?clock:Signal.signal -> ?clock_edge:Edge.t -> ?reset:Signal.signal -> ?reset_edge:Edge.t -> ?reset_to:Signal.signal -> ?clear:Signal.signal -> ?clear_level:Level.t -> ?clear_to:Signal.signal -> ?global_enable:Signal.signal -> t -> t
Sourceval clock : t -> Signal.signal
Sourceval clear : t -> Signal.signal
Sourceval reset : t -> Signal.signal
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