package hardcaml
RTL Hardware Design in OCaml
Install
Dune Dependency
Authors
Maintainers
Sources
v0.17.0.tar.gz
sha256=925bbc1f25dabcdea9cd6dc484badf689dc5dd18e511b6d105c4d7582cb29237
Description
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Published: 26 May 2024
README
"Hardcaml"

Hardcaml is an OCaml library for designing and testing hardware designs.
- Express hardware designs in OCaml
- Make generic designs using higher order functions, lists, maps, functors...
- Simulate designs in OCaml
- Convert to (hierarchical) Verilog or VHDL
- Write new modules to transform or analyse circuits, or provide new backends
Install
$ opam install hardcaml ppx_hardcaml hardcaml_waveterm
Documentation
Tools and libraries
Hardcaml_waveterm
- ASCII based digital waveforms. Usable in expect tests or from an interactive terminal application.Hardcaml_c
- convert Hardcaml designs to C-based simulation models. Provides an API compatible with the standard Cyclesim module. Trades compilation time for runtime performance.Hardcaml_verilator
- Convert Hardcaml designs to very high speed simulation model using the open source Verilator compiler.Hardcaml_step_testbench
- Monadic testbench API. Control multiple tasks synchronized to a clock without converting to a statemachine coding style.Hardcaml_circuits
- A library of useful/interesting Hardcaml designsHardcaml_fixed_point
- Fixed point arithmetic with rounding and overflow controlHardcaml_xilinx
- Various Xilinx primitives wrapped with Hardcaml interfaces and simulation modelsHardcaml_xilinx_components
- Tool to read Xilinx unisim and xpm component definitions and generate Hardcaml interfacesHardcaml_of_verilog
- Convert a verilog design to Hardcaml using YosysHardcaml_verify
- SAT based formal verification tools for HardcamlHardcaml_xilinx_reports
- Automated generation of synthesis reports from Vivado.
Projects using Hardcaml
Hardcaml ZPrize
- Multi-scalar Multiplication and Number Theoretic Transform accelerators.Hardcaml Mips
- A simple 5-stage MIPs CPU with associated blog detailing the development process.Hardcaml_arty
- Infrastructure targeting the Arty A7 board.Hardcaml Reed-Solomon
- Configurable Reed-Solomon encoder and decoder implementation.Hardcaml JPEG
- JPEG decoder design.
Dependencies (10)
-
zarith
>= "1.11"
-
ppxlib
>= "0.28.0" & < "0.36.0"
-
dune
>= "3.11.0"
-
stdio
>= "v0.17" & < "v0.18"
-
ppx_sexp_conv
>= "v0.17" & < "v0.18"
-
ppx_jane
>= "v0.17" & < "v0.18"
-
core_kernel
>= "v0.17" & < "v0.18"
-
bin_prot
>= "v0.17" & < "v0.18"
-
base
>= "v0.17" & < "v0.18"
-
ocaml
>= "5.1.0"
Dev Dependencies
None
Used by (16)
- hardcaml-lua
-
hardcaml_axi
>= "v0.17.0"
-
hardcaml_c
>= "v0.17.0"
-
hardcaml_circuits
>= "v0.17.0"
- hardcaml_event_driven_sim
-
hardcaml_fixed_point
>= "v0.17.0"
-
hardcaml_handshake
>= "v0.17.0"
-
hardcaml_of_verilog
>= "v0.17.0"
-
hardcaml_step_testbench
>= "v0.17.0"
-
hardcaml_verify
>= "v0.17.0"
-
hardcaml_verilator
>= "v0.17.0"
-
hardcaml_waveterm
>= "v0.17.0"
-
hardcaml_xilinx
>= "v0.17.0"
-
hardcaml_xilinx_components
>= "v0.17.0"
-
hardcaml_xilinx_reports
>= "v0.17.0"
- ppx_hardcaml
Conflicts
None
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