package hardcaml-yosys

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type !'a t = {
  1. abits : 'a;
  2. init : 'a;
  3. memid : 'a;
  4. offset : 'a;
  5. size : 'a;
  6. width : 'a;
  7. rd_clk_enable : 'a;
  8. rd_clk_polarity : 'a;
  9. rd_ports : 'a;
  10. rd_transparent : 'a;
  11. wr_clk_enable : 'a;
  12. wr_clk_polarity : 'a;
  13. wr_ports : 'a;
}
val t : (string * int) t
val map : ('a -> 'b) -> 'a t -> 'b t
val map2 : ('a -> 'b -> 'c) -> 'a t -> 'b t -> 'c t
val to_list : 'a t -> 'a list
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