package diffast-langs-verilog

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  2. Docs
Verilog parser plugin for Diff/AST

Install

Dune Dependency

github.com Readme Edit opam file Versions (2)

Authors

  1. C
    Codinuum <codinuum@me.com>
  2. M
    Masatomo Hashimoto <m.hashimoto@stair.center>

Maintainers

  1. C
    Codinuum <codinuum@me.com>
  2. M
    Masatomo Hashimoto <m.hashimoto@stair.center>

Sources

v0.2.tar.gz
sha256=b5bc3e9ed7c92912e06be663c904b6d8c7d277828b6442e43d57c64414d9c5ab
md5=7404586197ede6a4f0a0d00a69069b37

doc/diffast-langs-verilog.base/Verilog_base/V_label/index.html

Module Verilog_base.V_labelSource

module Loc = Diffast_misc.Loc
module Astml = Diffast_core.Astml
module Lang_base = Diffast_core.Lang_base
module Spec = Diffast_core.Spec
module Charpool = Diffast_core.Charpool
Sourcemodule Ls = Labels
Sourcetype identifier = string
Sourceval lang_prefix : string
Sourceval keyroot_depth_min : int
Sourceval null_tid : string * string
Sourceval mktid : 'a -> 'b -> 'a * 'b
Sourceval tid_to_string : (string * string) -> string
Sourceval anonymize_tid : ?more:bool -> Lang_base.tie_id -> string * string
Sourceval mktidattr : Lang_base.tie_id -> (string * string) list
Sourcemodule type T = sig ... end
Sourceval conv_loc : Ast.Loc.t -> Loc.t
Sourcemodule OverloadOperator : sig ... end
Sourcemodule AssignmentOperator : sig ... end
Sourcemodule IncOrDecOperator : sig ... end
Sourcemodule UnaryOperator : sig ... end
Sourcemodule BinaryOperator : sig ... end
Sourcemodule TimingCheck : sig ... end
Sourcemodule SystemTask : sig ... end
Sourcemodule Qualifier : sig ... end
Sourcemodule NetType : sig ... end
Sourcemodule PortDirection : sig ... end
Sourcemodule Gate : sig ... end
Sourcemodule DataType : sig ... end
Sourcemodule Expression : sig ... end
Sourcemodule EventExpression : sig ... end
Sourcemodule PropertyExpression : sig ... end
Sourcemodule SequenceExpression : sig ... end
Sourcemodule JoinSpec : sig ... end
Sourcemodule Statement : sig ... end
Sourcemodule CompilerDirective : sig ... end
Sourcemodule Strength : sig ... end
Sourcemodule SimpleImmediateAssertion : sig ... end
Sourcemodule ConcurrentAssertion : sig ... end
Sourcemodule ModuleSpec : sig ... end
Sourcemodule AlwaysSpec : sig ... end
Sourcemodule BinsSpec : sig ... end
Sourcetype annotation = string option
Sourceval null_annotation : 'a option
Sourceval annotation_to_string : string option -> string
include module type of struct include Label end
Sourcetype t = Verilog_parsing.Label.t =
  1. | Dummy
  2. | Error
  3. | Empty
  4. | SourceText
  5. | LibraryText
  6. | CompilerDirective of Verilog_parsing.Labels.CompilerDirective.t
  7. | ModuleDeclaration of Verilog_parsing.Labels.ModuleSpec.t * Verilog_parsing.Common.identifier
  8. | UdpDeclaration of Verilog_parsing.Common.identifier
  9. | NetDeclaration of Verilog_parsing.Common.identifier list
  10. | BindDirective of Verilog_parsing.Common.identifier
  11. | Expr of Verilog_parsing.Labels.Expression.t
  12. | Stmt of Verilog_parsing.Labels.Statement.t
  13. | NetType of Verilog_parsing.Labels.NetType.t
  14. | LocalParameterDeclaration of Verilog_parsing.Common.identifier list
  15. | ParameterDeclaration of Verilog_parsing.Common.identifier list
  16. | ParameterPortDeclaration
  17. | ModuleBody
  18. | Instantiation of Verilog_parsing.Common.identifier
  19. | GateInstantiation of Verilog_parsing.Labels.Gate.t
  20. | ContinuousAssign
  21. | Assign
  22. | ConcurrentAssertionItem
  23. | DeferredImmediateAssertionItem
  24. | PpIdentifier of Verilog_parsing.Common.identifier
  25. | PackedDimension
  26. | ParamAssignment of Verilog_parsing.Common.identifier
  27. | DefparamAssignment
  28. | IdSelect of Verilog_parsing.Common.identifier
  29. | Select
  30. | Range
  31. | RangePlus
  32. | RangeMinus
  33. | RangeForeach
  34. | Root
  35. | This
  36. | Super
  37. | Cellpin of Verilog_parsing.Common.identifier
  38. | CellpinStar
  39. | CellpinAnon
  40. | DelayValue of Verilog_parsing.Common.identifier
  41. | PackageScope of Verilog_parsing.Common.identifier
  42. | PackageScopeUnit
  43. | PackageScopeLocal
  44. | PackageImport of Verilog_parsing.Common.identifier
  45. | PackageImportAny
  46. | LifetimeStatic
  47. | LifetimeAutomatic
  48. | EndLabel of Verilog_parsing.Common.identifier
  49. | EndLabelNew
  50. | ClassType of Verilog_parsing.Common.identifier
  51. | DataType of Verilog_parsing.Labels.DataType.t
  52. | ImplicitDataType
  53. | VarDeclAssignments
  54. | Signed
  55. | Unsigned
  56. | ArgsDotted of Verilog_parsing.Common.identifier
  57. | Tagged
  58. | StructUnionBody
  59. | StructUnionMember
  60. | ClassScopeId of Verilog_parsing.Common.identifier
  61. | Void
  62. | EnumNameDeclaration of Verilog_parsing.Common.identifier
  63. | EnumBody
  64. | IdClassSel of Verilog_parsing.Common.identifier
  65. | Variable of Verilog_parsing.Common.identifier
  66. | Extern
  67. | PackageImportDeclaration
  68. | PackageImportItem of Verilog_parsing.Common.identifier
  69. | Packed
  70. | ParameterValueAssignment
  71. | Ports
  72. | PortsStar
  73. | BitSelect
  74. | VariableDeclAssignment of Verilog_parsing.Common.identifier
  75. | DynamicArrayNew
  76. | VariableDimension
  77. | VariableDimensionStar
  78. | GenItemBegin
  79. | GenBlockId of Verilog_parsing.Common.identifier
  80. | GenerateRegion
  81. | Scalared
  82. | Vectored
  83. | DelayControl
  84. | NetSig of Verilog_parsing.Common.identifier
  85. | ParameterOverride
  86. | PortDeclaration
  87. | PortDirection of Verilog_parsing.Labels.PortDirection.t
  88. | Strength of Verilog_parsing.Labels.Strength.t
  89. | StrengthSupply0
  90. | StrengthSupply1
  91. | StrengthSpec
  92. | VarDataType
  93. | Port of Verilog_parsing.Common.identifier
  94. | InterfacePort of Verilog_parsing.Common.identifier
  95. | InterfacePortInterface
  96. | ModportIdentifier of Verilog_parsing.Common.identifier
  97. | PortMulti
  98. | ExprScope
  99. | ExprScopeThis
  100. | ExprScopeSuper
  101. | ExprScopeDot
  102. | ExprScopeDotSuper
  103. | CondPredicate
  104. | CondPattern
  105. | Dist
  106. | DistItem
  107. | DistWeight
  108. | DistWeightRange
  109. | ArrayRange
  110. | ArrayRangePlus
  111. | ArrayRangeMinus
  112. | CastingTypeSimple
  113. | CastingTypeSigned
  114. | CastingTypeUnsigned
  115. | CastingTypeString
  116. | CastingTypeConst
  117. | ValueRange
  118. | Pattern
  119. | PatternId of Verilog_parsing.Common.identifier
  120. | PatternStar
  121. | PatternTagged of Verilog_parsing.Common.identifier
  122. | EventControl
  123. | EventControlStar
  124. | EventControlParenStar
  125. | EventControlRepeat
  126. | EvExpr of Verilog_parsing.Labels.EventExpression.t
  127. | CaseItem
  128. | CaseItemDefault
  129. | CaseInsideItem
  130. | CaseInsideItemDefault
  131. | CaseItems
  132. | CaseItemsMatches
  133. | CaseItemsInside
  134. | With
  135. | Args
  136. | ConstraintBlock
  137. | ForInit
  138. | ForInitItemDT of Verilog_parsing.Common.identifier
  139. | ForInitItemLval
  140. | StreamingConcat
  141. | OrderRL
  142. | OrderLR
  143. | StreamConcat
  144. | Solve
  145. | SolveBefore
  146. | ActionBlock
  147. | CycleDelay of string
  148. | CycleDelayId of Verilog_parsing.Common.identifier
  149. | CycleDelayParen
  150. | Priority
  151. | Unique
  152. | Unique0
  153. | InstRange
  154. | InstName of Verilog_parsing.Common.identifier
  155. | PExpr of Verilog_parsing.Labels.PropertyExpression.t
  156. | ClockingEvent of Verilog_parsing.Common.identifier
  157. | ClockingEventParen
  158. | PropertyCase
  159. | PropertyCaseDefault
  160. | DisableIff
  161. | CycleDelayRange of string
  162. | CycleDelayRangeId of Verilog_parsing.Common.identifier
  163. | CycleDelayRangeParen
  164. | CycleDelayRangeBracket
  165. | CycleDelayRangeBracketStar
  166. | CycleDelayRangeBracketPlus
  167. | SExpr of Verilog_parsing.Labels.SequenceExpression.t
  168. | ConsecutiveRepetition
  169. | NonconsecutiveRepetition
  170. | GotoRepetition
  171. | NetAlias
  172. | InitialConstruct
  173. | FinalConstruct
  174. | AlwaysConstruct of Verilog_parsing.Labels.AlwaysSpec.t
  175. | ConcurrentAssertionItemLabeled of Verilog_parsing.Common.identifier
  176. | ConcurrentAssertionStmt of Verilog_parsing.Labels.ConcurrentAssertion.t
  177. | DeferredImmediateAssertionItemLabeled of Verilog_parsing.Common.identifier
  178. | DeferredImmediateAssertionStmt of Verilog_parsing.Labels.DeferredImmediateAssertion.t
  179. | SimpleImmediateAssertionStmt of Verilog_parsing.Labels.SimpleImmediateAssertion.t
  180. | CheckerInstantiation of Verilog_parsing.Common.identifier
  181. | LoopGenerateConstruct
  182. | GenvarDeclaration of Verilog_parsing.Common.identifier list
  183. | GenvarIterationAssign of Verilog_parsing.Labels.AssignmentOperator.t * Verilog_parsing.Common.identifier
  184. | GenvarIterationIncOrDec of Verilog_parsing.Labels.IncOrDecOperator.t * Verilog_parsing.Common.identifier
  185. | GenvarIdDecl of Verilog_parsing.Common.identifier
  186. | GenvarInitId of Verilog_parsing.Common.identifier
  187. | GenvarInit
  188. | SpecifyBlock
  189. | SpecparamDeclaration
  190. | SpecparamAssignmentId of Verilog_parsing.Common.identifier
  191. | SpecparamAssignmentPulseControl of Verilog_parsing.Common.identifier
  192. | PulsestyleDeclarationOnevent
  193. | PulsestyleDeclarationOndetect
  194. | ShowcancelledDeclaration
  195. | NoshowcancelledDeclaration
  196. | SpecifyTerminalDescriptor
  197. | InputOrOutputId of Verilog_parsing.Common.identifier
  198. | InterfaceIdentifier of Verilog_parsing.Common.identifier
  199. | ProgramDeclaration of Verilog_parsing.Common.identifier
  200. | InterfaceDeclaration of Verilog_parsing.Common.identifier
  201. | InterfaceDeclarationExtern of Verilog_parsing.Common.identifier
  202. | TimeUnitsDeclaration
  203. | TimeUnit of string
  204. | Timeprecision of string
  205. | PackageDeclaration of Verilog_parsing.Common.identifier
  206. | AnonymousProgram
  207. | AnonymousProgramItemEmpty
  208. | FunctionDeclaration of Verilog_parsing.Common.identifier
  209. | FunctionPrototype of Verilog_parsing.Common.identifier
  210. | FuncId of Verilog_parsing.Common.identifier
  211. | FuncIdVoid of Verilog_parsing.Common.identifier
  212. | FuncIdNew
  213. | TfIdScoped of Verilog_parsing.Common.identifier
  214. | TaskDeclaration of Verilog_parsing.Common.identifier
  215. | TaskPrototype of Verilog_parsing.Common.identifier
  216. | ClassCtorPrototype
  217. | TfPortListPart
  218. | TfBody
  219. | TfPortDeclaration
  220. | TfPortItemAssignment of Verilog_parsing.Common.identifier
  221. | TfPortItem
  222. | TfVariableIdentifier of Verilog_parsing.Common.identifier
  223. | CheckerDeclaration of Verilog_parsing.Common.identifier
  224. | PropertyDeclaration of Verilog_parsing.Common.identifier
  225. | PropertyDeclBody
  226. | PropertyPortItem
  227. | PropertyPortItemDir
  228. | PropertyPortItemAssignment of Verilog_parsing.Common.identifier
  229. | SequenceDeclaration of Verilog_parsing.Common.identifier
  230. | SequenceDeclBody
  231. | LetDeclaration of Verilog_parsing.Common.identifier
  232. | PropertyStatementSpec
  233. | AssertionVariableDeclaration
  234. | SequenceFormalTypeSequence
  235. | SequenceFormalTypeUntyped
  236. | DataDeclarationVar
  237. | Const
  238. | DataDeclarationVarClass
  239. | TypeDeclaration of Verilog_parsing.Common.identifier
  240. | ScopedType of Verilog_parsing.Common.identifier
  241. | TypeIdentifier of Verilog_parsing.Common.identifier
  242. | TypeDeclEnum
  243. | TypeDeclStruct
  244. | TypeDeclUnion
  245. | TypeDeclClass
  246. | VirtualInterfaceDeclaration of Verilog_parsing.Common.identifier
  247. | ModportDeclaration of Verilog_parsing.Common.identifier list
  248. | ModportItem of Verilog_parsing.Common.identifier
  249. | ModportSimplePortsDecl
  250. | ModportClockingDecl of Verilog_parsing.Common.identifier
  251. | ModportTfPortsDeclImport
  252. | ModportTfPortsDeclExport
  253. | ModportSimplePort of Verilog_parsing.Common.identifier
  254. | ModportSimplePortDot of Verilog_parsing.Common.identifier
  255. | ModportTfPort of Verilog_parsing.Common.identifier
  256. | CovergroupDeclaration of Verilog_parsing.Common.identifier
  257. | Paren
  258. | CoverageOption of Verilog_parsing.Common.identifier * Verilog_parsing.Common.identifier
  259. | CoverPoint
  260. | CoverPointLabeled of Verilog_parsing.Common.identifier
  261. | CoverCross
  262. | CoverCrossLabeled of Verilog_parsing.Common.identifier
  263. | CrossItem of Verilog_parsing.Common.identifier
  264. | Iff
  265. | BinsList
  266. | BinsEmpty
  267. | SelectBins
  268. | SelectBinsEmpty
  269. | Bins of Verilog_parsing.Labels.BinsSpec.t * Verilog_parsing.Common.identifier
  270. | BinsSelection of Verilog_parsing.Labels.BinsSpec.t * Verilog_parsing.Common.identifier
  271. | BinsExpressionVar of Verilog_parsing.Common.identifier
  272. | BinsExpression of Verilog_parsing.Common.identifier * Verilog_parsing.Common.identifier
  273. | NBins
  274. | SelCondBinsof
  275. | SelExprNot
  276. | SelExprAnd
  277. | SelExprOr
  278. | SelExprParen
  279. | Intersect
  280. | Wildcard
  281. | TransSet
  282. | TransRangeList
  283. | RepeatRange
  284. | TransItem
  285. | TransRepetitionConsecutive
  286. | TransRepetitionNonconsecutive
  287. | TransRepetitionGoto
  288. | Default
  289. | DefaultSequence
  290. | OpenRangeList
  291. | CoverageEventWith of Verilog_parsing.Common.identifier
  292. | CoverageEventBlockEvent
  293. | BlockEventExpression
  294. | BlockEventExpressionBegin
  295. | BlockEventExpressionEnd
  296. | HierarchicalBtfIdentifier of Verilog_parsing.Common.identifier
  297. | PackageExportDeclarationStar
  298. | PackageExportDeclaration
  299. | DpiImport of string
  300. | DpiExportFunc of string * Verilog_parsing.Common.identifier
  301. | DpiExportTask of string * Verilog_parsing.Common.identifier
  302. | DpiImportLabel of Verilog_parsing.Common.identifier
  303. | DpiTfImportPropertyContext
  304. | DpiTfImportPropertyPure
  305. | ExternConstraintDeclaration
  306. | Static
  307. | Virtual
  308. | ClassDeclaration of Verilog_parsing.Common.identifier
  309. | ClassExtends
  310. | ClassItemEmpty
  311. | ClassMethod
  312. | Qualifier of Verilog_parsing.Labels.Qualifier.t
  313. | ClassBody
  314. | ClassConstraint of Verilog_parsing.Common.identifier
  315. | Pure
  316. | ClassProperty
  317. | PackageOrGenerateItemEmpty
  318. | Forkjoin
  319. | ExternTfDeclaration of Verilog_parsing.Common.identifier
  320. | TimingCheck of Verilog_parsing.Labels.TimingCheck.t
  321. | SystemTimingCheck
  322. | Notifier of Verilog_parsing.Common.identifier
  323. | Delayed of Verilog_parsing.Common.identifier
  324. | TimingCheckEvent
  325. | TimingCheckEventControlPosedge
  326. | TimingCheckEventControlNegedge
  327. | TimingCheckEventControl
  328. | EdgeDescriptor of string
  329. | OverloadDeclaration of Verilog_parsing.Labels.OverloadOperator.t * Verilog_parsing.Common.identifier
  330. | Params
  331. | ClockingDeclaration of Verilog_parsing.Common.identifier
  332. | Global
  333. | ClockingBody
  334. | ClockingItemDefault
  335. | ClockingItem
  336. | DefaultSkewInput
  337. | DefaultSkewOutput
  338. | DefaultSkewInputOutput
  339. | ClockingDirectionInput
  340. | ClockingDirectionInputOutput
  341. | ClockingDirectionInout
  342. | ClockingSkewPosedge
  343. | ClockingSkewNegedge
  344. | ClockingSkewEdge
  345. | ClockingSkew
  346. | ClockingDeclAssign of Verilog_parsing.Common.identifier
  347. | Production of Verilog_parsing.Common.identifier
  348. | ProductionItem of Verilog_parsing.Common.identifier
  349. | RsCodeBlock
  350. | RsRule
  351. | RsProductionList
  352. | RsProductionListRandJoin
  353. | WeightSpecInt of string
  354. | WeightSpecId
  355. | WeightSpec
  356. | RsProdIf
  357. | RsProdRepeat
  358. | RsProdCase
  359. | RsCaseItem
  360. | RsCaseItemDefault
  361. | CheckerOrGenerateItemEmpty
  362. | ConditionalGenerateConstructCase
  363. | ConditionalGenerateConstructIf
  364. | ElaborationSystemTask of Verilog_parsing.Labels.SystemTask.t
  365. | CaseGenerateItem
  366. | CaseGenerateItemDefault
  367. | AssignmentPattern
  368. | AssignmentPatternExpr
  369. | PatternKey
  370. | PatternKeyDefault
  371. | PatternMember
  372. | SimplePathDeclaration
  373. | ParallelPathDescription
  374. | FullPathDescription
  375. | PathInputs
  376. | PathOutputs
  377. | PathDelayValue
  378. | PolarityPlus
  379. | PolarityMinus
  380. | EdgePosedge
  381. | EdgeNegedge
  382. | EdgeSensitivePathDeclaration
  383. | ParallelEdgeSensitivePathDescription
  384. | FullEdgeSensitivePathDescription
  385. | ParallelEdgeSensitivePathDescriptionSub
  386. | FullEdgeSensitivePathDescriptionSub
  387. | StateDependentPathDeclarationIf
  388. | StateDependentPathDeclarationIfnone
  389. | VariableLvalue
  390. | AttributeInstance
  391. | AttrSpec of Verilog_parsing.Common.identifier
  392. | UdpPort of Verilog_parsing.Common.identifier
  393. | UdpPortDeclaration
  394. | UdpOutputDeclaration of Verilog_parsing.Common.identifier
  395. | UdpOutputDeclarationReg of Verilog_parsing.Common.identifier
  396. | UdpInputDeclaration
  397. | UdpRegDeclaration of Verilog_parsing.Common.identifier
  398. | SequentialBody
  399. | CombinationalBody
  400. | UdpInitialStmt of Verilog_parsing.Common.identifier * string
  401. | SequentialEntry
  402. | EdgeIndicator
  403. | EdgeSymbol of string
  404. | LevelSymbol of string
  405. | OutputSymbol of string
  406. | CombinationalEntry
  407. | NextStateMinus
  408. | UdpPortsStar
  409. | UdpPorts
  410. | UdpPortDecls
  411. | UdpDeclarationPorts
  412. | AttributeInstances
  413. | ConfigDeclaration of Verilog_parsing.Common.identifier
  414. | DesignStatement
  415. | CellId of Verilog_parsing.Common.identifier
  416. | LibraryIdentifier of Verilog_parsing.Common.identifier
  417. | LiblistClause
  418. | CellClause of Verilog_parsing.Common.identifier
  419. | UseClause
  420. | ColonConfig
  421. | InstanceName
  422. | InstanceIdentifier of Verilog_parsing.Common.identifier
  423. | TopModuleIdentifier of Verilog_parsing.Common.identifier
  424. | InstClause
  425. | ConfigRuleStatementDefault
  426. | ConfigRuleStatement
  427. | LibraryDeclaration of Verilog_parsing.Common.identifier
  428. | Incdir
  429. | FilePathSpec of string
  430. | IncludeStatement of string
  431. | PragmaExpression of Verilog_parsing.Common.identifier
  432. | PragmaValueTuple
  433. | PragmaValueNum of string
  434. | PragmaValueStr of string
  435. | PragmaValueId of Verilog_parsing.Common.identifier
  436. | PackageImportDecls
  437. | ParamPorts
  438. | Ranges
  439. | VariableDimensions
  440. | CaseConds
  441. | NetDeclAssignments of Verilog_parsing.Common.identifier list
  442. | ParamAssignments of Verilog_parsing.Common.identifier list
  443. | MacroExpr of string
  444. | MacroStmt of string
  445. | Var
Sourceval to_string : t -> string
Sourceval to_simple_string : t -> Verilog_parsing.Common.identifier
Sourceval to_tag : ?strip:bool -> t -> string * (string * Verilog_parsing.Common.identifier) list
Sourceval get_identifiers : t -> Verilog_parsing.Common.identifier list
Sourceval pexpr_to_stmt : t -> t
Sourceval expr_to_stmt : t -> t
Sourceval expr_of_integral_number : string -> t
Sourceval expr_uo : Verilog_parsing__Labels.UnaryOperator.t -> t
Sourceval expr_bo : Verilog_parsing__Labels.BinaryOperator.t -> t
Sourceval expr_ao : Verilog_parsing__Labels.AssignmentOperator.t -> t
Sourceval stmt_ao : Verilog_parsing__Labels.AssignmentOperator.t -> t
Sourceval is_error : t -> bool
Sourceval strip : 'a -> 'a
Sourceval anonymize : ?more:bool -> t -> t
Sourceval anonymize2 : t -> t
Sourceval anonymize3 : t -> t
Sourceval to_short_string : ?ignore_identifiers_flag:bool -> t -> string
Sourceval is_hunk_boundary : 'a -> 'b -> bool
Sourceval forced_to_be_collapsible : 'a -> bool
Sourceval is_collapse_target : < no_collapse_flag : bool.. > -> t -> bool
Sourceval is_to_be_notified : t -> bool
Sourceval is_boundary : t -> bool
Sourceval is_partition : t -> bool
Sourceval is_sequence : t -> bool
Sourceval is_ntuple : 'a -> bool
Sourceval get_category : t -> string
Sourceval get_name : ?strip:bool -> t -> Verilog_parsing.Common.identifier
Sourceval get_value : t -> string
Sourceval has_value : t -> bool
Sourceval has_non_trivial_value : t -> bool
Sourceval has_non_trivial_tid : 'a -> bool
Sourceval is_compatible : ?weak:bool -> 'a -> 'b -> bool
Sourceval is_order_insensitive : 'a -> bool
Sourceval quasi_eq : 'a -> 'b -> bool
Sourceval relabel_allowed : (t * t) -> bool
Sourceval move_disallowed : 'a -> bool
Sourceval is_common : 'a -> bool
Sourceval to_char : 'a -> char
Sourceval has_names : t -> bool
Sourceval has_a_name : t -> bool
Sourceval is_named : t -> bool
Sourceval is_named_orig : t -> bool
Sourceval to_elem_data : ?strip:bool -> ?afilt:(string -> bool) -> Astml.Loc.t -> t -> string * (string * string) list * string
Sourceval of_elem_data : 'a -> 'b -> 'c -> t
Sourceval getlab : < data : < _label : Obj.t.. >.. > -> t
Sourceval cannot_be_keyroot : < data : < _label : Obj.t.. >.. > -> bool
Sourceval is_string_literal : 'a -> bool
Sourceval is_int_literal : 'a -> bool
Sourceval is_real_literal : 'a -> bool
Sourceval is_phantom : t -> bool
Sourceval is_special : 'a -> bool
Sourceval is_always_construct : t -> bool
Sourceval is_timing_control : t -> bool
Sourceval is_continuous_assign : t -> bool
Sourceval is_blocking_assign : t -> bool
Sourceval is_non_blocking_assign : t -> bool
Sourceval is_if : t -> bool
Sourceval is_case : t -> bool
Sourceval is_case_item : t -> bool
Sourceval is_case_cond : t -> bool
Sourceval is_module_decl : t -> bool
Sourceval is_ports : t -> bool
Sourceval is_port : t -> bool
Sourceval is_port_dir : t -> bool
Sourceval is_net_type : t -> bool
Sourceval is_data_type : t -> bool
Sourceval is_var_data_type : t -> bool
Sourceval is_signing : t -> bool
Sourceval is_ranges : t -> bool
Sourceval is_variable_dims : t -> bool
Sourceval is_inst : t -> bool
Sourceval is_initial_construct : t -> bool
Sourceval is_final_construct : t -> bool
Sourceval is_generate_region : t -> bool
Sourceval is_param_port_decl : t -> bool
Sourceval is_param_assign : t -> bool
Sourceval is_data_decl_var : t -> bool
Sourceval is_net_decl : t -> bool
Sourceval is_reg : t -> bool
Sourceval is_wire : t -> bool
Sourceval is_expr : t -> bool
Sourceval is_op : 'a -> bool
Sourceval is_scope_creating : 'a -> bool
Sourceval is_stmt : t -> bool
Sourceval is_statement : t -> bool
Sourceval is_primary : 'a -> bool
Sourceval is_block : 'a -> bool
Sourceval is_pp_define : t -> bool
Sourceval is_pp_include : t -> bool
Sourceval is_source_text : t -> bool
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